3/02/2012

Modeling, Verification and Exploration of Task-Level Review

Modeling, Verification and Exploration of Task-Level
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This book is -almost- worth it's price. I have used it in melding the implementation of hardware, software, HDL simulation and co-verification into a cohesive solution. Modeling can be an exercise in attaining perfection. In some dedicated modeling environments this is not the need. This book lays the path toward assuring the need for your specific design is properly addressed.

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The combination of VLSI process technology and real-timedigital signal processing (DSP) has brought a break-through ininformation technology. This rapid technical (r)evolution allows theintegration of ever more complex systems on a single chip. However,these technology and integration advances have not been matched by anincrease in design productivity, causing technology to leapfrog thedesign of integrated circuits (ICs). The success of these emerging`systems-on-a-chip' (SOC) can only be guaranteed by a systematic andformal design methodology, possibly automated in computer-aided design(CAD) tools, and effective re-use of existing intellectual property(IP). In this book, a contribution is made to the modeling, timingverification and analysis, and the automatic synthesis of integratedreal-time DSP systems. Existing literature in these three domains isextensively reviewed, making this book the first to give acomprehensive overview of existing techniques. The emphasis throughoutthe book is on the support and guaranteeing of the real-time aspectand constraints of these systems, which avoids time consuming designiterations and safeguards the ever shrinking time-to-market. The proposed `Multi-Thread Graph' (MTG) system model featurestwo-layers, unifying a (timed) Petri net and a control-data flowgraph. Its unique interface between both models offers the best of twoworlds and introduces an extra abstraction level hiding theoperation-level details which are unnecessary during global systemexploration. The formulated timing analysis and verification approachsupports the calculation of temporal separation between different MTGentities as well as realistic performance metrics for highlyconcurrent systems. The synthesis methodology focuses on managing thetask-level concurrency (i.e. task scheduling), as part of a proposedoverall system design meta flow. It emphasizes performance and timingaspects (`timeliness'), while minimizing processor cost overhead asdriven by high-level cost estimators. The approach is new in theabstraction level it employs, and in its optimal hybrid dynamic/staticscheduling policy which, driven by cost estimators, selects thescheduling policy for each behavior. At the low-level, RTOS synthesisgenerates an application-specific scheduler for the softwarecomponent. The proposed synthesis methodology (at the task-level) is asserted toyield most optimal results when employed before the hardware/softwarepartition is made. At this level, the distinction between these two isminimal, such that all steps in the design trajectory can be shared,thereby reducing the system cost significantly and allowing tightersatisfaction of timing/performance constraints.From the Foreword: This book is the first comprehensivetreatment of software, and more general, system, generation(synthesis) techniques based on formal models. It can be used as avery valuable reference to understand the development of the field ofembedded software design, and of system design and synthesis ingeneral. The book offers an invaluable help to researchers andpractitioners of the field of embedded system design. Prof. AlbertoSangiovanni-Vincentelli, Edgar L. and Harold H. Buttner Professor ofElectrical Engineering and Computer Science , University ofCalifornia, Berkeley, Chief Technology Advisor, Cadence DesignSystems.

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