SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling Review

Average Reviews:

(More customer reviews)(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction.
You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog.
As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference.
And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.)

Click Here to see more reviews about: SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

Get 20% OFF

Click here for more information about SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling