Showing posts with label systemverilog. Show all posts
Showing posts with label systemverilog. Show all posts

5/27/2012

Principles of Functional Verification Review

Principles of Functional Verification
Average Reviews:

(More customer reviews)
Instead of attempting to teach you the "howtos" of functional verification this book teaches you the "whys". This causes it to be much less like a textbook than many others on the same subject. Therefore reading this book cover to cover is relatively easy and useful. Examples given are at the appropriate level of complexity - neither too simple nor too complex.
Readers of this book could easily range from senior management to test coders. Senior management would learn the purposes behind various aspects of functional verification and why the cost and complexity continues to rise. Engineers would be exposed to the reasoning behind the use of some functional verification techniques.
Each chapter discusses the ideas behind some aspects of functional verification with examples of how this might be used in an actual system being verified. There are few code examples since that would not contribute to the purpose of the book. The examples are primarily system architectures and how a specific component of functional verification would be used in testing that architecture.
The list of subjects covered is complete relative to the current state of the art.
Overall this is a very useful book to read. I would suggest that most verification engineers and their managers would benefit from exposure to this book. Even if you know all of this already it is a good book to have available to explain to other people what you are doing.

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As design complexity in chips and devices continues to rise, so, too, does the demand for functional verification. Principles of Functional Verification is a hands-on, practical text that will help train professionals in the field of engineering on the methodology and approaches to verification.In practice, the architectural intent of a device is necessarily abstract. The implementation process, however, must define the detailed mechanisms to achieve the architectural goals. Based on a decade of experience, Principles of Functional Verification intends to pinpoint the issues, provide strategies to solve the issues, and present practical applications for narrowing the gap between architectural intent and implementation. The book is divided into three parts, each building upon the chapters within the previous part. Part One addresses why functional verification is necessary, its definition and goals. In Part Two, the heart of the methodology and approaches to solving verification issues are examined. Each chapter in this part ends with exercises to apply what was discussed in the chapter. Part Three looks at practical applications, discussing project planning, resource requirements, and costs. Each chapter throughout all three parts will open with Key Objectives, focal points the reader can expect to review in the chapter. * Takes a "holistic" approach to verification issues* Approach is not restricted to one language* Discussed the verification process, not just how to use the verification language

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10/23/2011

SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling Review

SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling
Average Reviews:

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(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction.
You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog.
As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference.
And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.)

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In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

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